Abstract
Nowadays the toolchain for innovating wireless systems technology has a high growth rate with the inclusion of prototyping radio systems. The trend is to migrate toward Software Defined Radio (SDR) devices due to low complexity design, implementation, and speed of data transmission of radio resources. In this context, we highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation. The digital filter Type 2 is adapted to the PLL scheme to improve the Time to Achieve Lock and reduce the steady-state error. In addition, we evaluate the filter design into PLL scheme with an RTL-SDR device to demonstrate the performance noise in the receive signal; consequently, this is adapted to other high-performance FPGA technologies for radio signal processing.
Original language | English |
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Title of host publication | Intelligent Technologies |
Subtitle of host publication | Design and Applications for Society - Proceedings of CITIS 2022 |
Editors | Vladimir Robles-Bykbaev, Josefa Mula, Gilberto Reynoso-Meza |
Publisher | Springer Science and Business Media Deutschland GmbH |
Pages | 182-190 |
Number of pages | 9 |
ISBN (Print) | 9783031243264 |
DOIs | |
State | Published - 2023 |
Event | 8th International Conference on Science, Technology and Innovation for Society, CITIS 2022 - Guayaquil, Ecuador Duration: 22 Jun 2022 → 24 Jun 2022 |
Publication series
Name | Lecture Notes in Networks and Systems |
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Volume | 607 LNNS |
ISSN (Print) | 2367-3370 |
ISSN (Electronic) | 2367-3389 |
Conference
Conference | 8th International Conference on Science, Technology and Innovation for Society, CITIS 2022 |
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Country/Territory | Ecuador |
City | Guayaquil |
Period | 22/06/22 → 24/06/22 |
Bibliographical note
Publisher Copyright:© 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.
Keywords
- 5G/6G
- Loop Filter
- PLL
- RTL-SDR
- Steady state