Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems

Andres Ortega, Juan Inga, Diego Lamadrid

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Nowadays the toolchain for innovating wireless systems technology has a high growth rate with the inclusion of prototyping radio systems. The trend is to migrate toward Software Defined Radio (SDR) devices due to low complexity design, implementation, and speed of data transmission of radio resources. In this context, we highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation. The digital filter Type 2 is adapted to the PLL scheme to improve the Time to Achieve Lock and reduce the steady-state error. In addition, we evaluate the filter design into PLL scheme with an RTL-SDR device to demonstrate the performance noise in the receive signal; consequently, this is adapted to other high-performance FPGA technologies for radio signal processing.

Original languageEnglish
Title of host publicationLecture Notes in Networks and Systems
Subtitle of host publicationDesign and Applications for Society - Proceedings of CITIS 2022
EditorsVladimir Robles-Bykbaev, Josefa Mula, Gilberto Reynoso-Meza
PublisherSpringer Science and Business Media Deutschland GmbH
Pages182-190
Number of pages9
ISBN (Print)9783031243264
DOIs
StatePublished - 2023
Event8th International Conference on Science, Technology and Innovation for Society, CITIS 2022 - Guayaquil, Ecuador
Duration: 22 Jun 202224 Jun 2022

Publication series

NameLecture Notes in Networks and Systems
Volume607 LNNS

Conference

Conference8th International Conference on Science, Technology and Innovation for Society, CITIS 2022
Country/TerritoryEcuador
CityGuayaquil
Period22/06/2224/06/22

Bibliographical note

Publisher Copyright:
© 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

Keywords

  • 5G/6G
  • Loop Filter
  • PLL
  • RTL-SDR
  • Steady state

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