Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems

Andres Ortega; Juan Inga; Diego Lamadrid

doi:10.1007/978-3-031-24327-1_16

Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems

Andres Ortega, Juan Inga, Diego Lamadrid

Grupo de Investigación en Telecomunicaciones y Telemática (GITEL)

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución de conferencia › revisión exhaustiva

Resumen

Nowadays the toolchain for innovating wireless systems technology has a high growth rate with the inclusion of prototyping radio systems. The trend is to migrate toward Software Defined Radio (SDR) devices due to low complexity design, implementation, and speed of data transmission of radio resources. In this context, we highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation. The digital filter Type 2 is adapted to the PLL scheme to improve the Time to Achieve Lock and reduce the steady-state error. In addition, we evaluate the filter design into PLL scheme with an RTL-SDR device to demonstrate the performance noise in the receive signal; consequently, this is adapted to other high-performance FPGA technologies for radio signal processing.

Idioma original	Inglés
Título de la publicación alojada	Intelligent Technologies
Subtítulo de la publicación alojada	Design and Applications for Society - Proceedings of CITIS 2022
Editores	Vladimir Robles-Bykbaev, Josefa Mula, Gilberto Reynoso-Meza
Editorial	Springer Science and Business Media Deutschland GmbH
Páginas	182-190
Número de páginas	9
ISBN (versión impresa)	9783031243264
DOI	https://doi.org/10.1007/978-3-031-24327-1_16
Estado	Publicada - 2023
Evento	8th International Conference on Science, Technology and Innovation for Society, CITIS 2022 - Guayaquil, Ecuador Duración: 22 jun. 2022 → 24 jun. 2022

Serie de la publicación

Nombre	Lecture Notes in Networks and Systems
Volumen	607 LNNS
ISSN (versión impresa)	2367-3370
ISSN (versión digital)	2367-3389

Conferencia

Conferencia	8th International Conference on Science, Technology and Innovation for Society, CITIS 2022
País/Territorio	Ecuador
Ciudad	Guayaquil
Período	22/06/22 → 24/06/22

Nota bibliográfica

Publisher Copyright:
© 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

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10.1007/978-3-031-24327-1_16

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Ortega, A., Inga, J., & Lamadrid, D. (2023). Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems. En V. Robles-Bykbaev, J. Mula, & G. Reynoso-Meza (Eds.), Intelligent Technologies: Design and Applications for Society - Proceedings of CITIS 2022 (pp. 182-190). (Lecture Notes in Networks and Systems; Vol. 607 LNNS). Springer Science and Business Media Deutschland GmbH. https://doi.org/10.1007/978-3-031-24327-1_16

Ortega, Andres ; Inga, Juan ; Lamadrid, Diego. / Discrete Loop Filter for Time-Synchronization : An Approach from Design to Real Implementation with RTL-SDR Systems. Intelligent Technologies: Design and Applications for Society - Proceedings of CITIS 2022. editor / Vladimir Robles-Bykbaev ; Josefa Mula ; Gilberto Reynoso-Meza. Springer Science and Business Media Deutschland GmbH, 2023. pp. 182-190 (Lecture Notes in Networks and Systems).

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title = "Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems",

abstract = "Nowadays the toolchain for innovating wireless systems technology has a high growth rate with the inclusion of prototyping radio systems. The trend is to migrate toward Software Defined Radio (SDR) devices due to low complexity design, implementation, and speed of data transmission of radio resources. In this context, we highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation. The digital filter Type 2 is adapted to the PLL scheme to improve the Time to Achieve Lock and reduce the steady-state error. In addition, we evaluate the filter design into PLL scheme with an RTL-SDR device to demonstrate the performance noise in the receive signal; consequently, this is adapted to other high-performance FPGA technologies for radio signal processing.",

keywords = "5G/6G, Loop Filter, PLL, RTL-SDR, Steady state",

author = "Andres Ortega and Juan Inga and Diego Lamadrid",

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Ortega, A, Inga, J & Lamadrid, D 2023, Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems. En V Robles-Bykbaev, J Mula & G Reynoso-Meza (eds.), Intelligent Technologies: Design and Applications for Society - Proceedings of CITIS 2022. Lecture Notes in Networks and Systems, vol. 607 LNNS, Springer Science and Business Media Deutschland GmbH, pp. 182-190, 8th International Conference on Science, Technology and Innovation for Society, CITIS 2022, Guayaquil, Ecuador, 22/06/22. https://doi.org/10.1007/978-3-031-24327-1_16

Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems. / Ortega, Andres; Inga, Juan; Lamadrid, Diego.
Intelligent Technologies: Design and Applications for Society - Proceedings of CITIS 2022. ed. / Vladimir Robles-Bykbaev; Josefa Mula; Gilberto Reynoso-Meza. Springer Science and Business Media Deutschland GmbH, 2023. p. 182-190 (Lecture Notes in Networks and Systems; Vol. 607 LNNS).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución de conferencia › revisión exhaustiva

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N2 - Nowadays the toolchain for innovating wireless systems technology has a high growth rate with the inclusion of prototyping radio systems. The trend is to migrate toward Software Defined Radio (SDR) devices due to low complexity design, implementation, and speed of data transmission of radio resources. In this context, we highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation. The digital filter Type 2 is adapted to the PLL scheme to improve the Time to Achieve Lock and reduce the steady-state error. In addition, we evaluate the filter design into PLL scheme with an RTL-SDR device to demonstrate the performance noise in the receive signal; consequently, this is adapted to other high-performance FPGA technologies for radio signal processing.

AB - Nowadays the toolchain for innovating wireless systems technology has a high growth rate with the inclusion of prototyping radio systems. The trend is to migrate toward Software Defined Radio (SDR) devices due to low complexity design, implementation, and speed of data transmission of radio resources. In this context, we highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation. The digital filter Type 2 is adapted to the PLL scheme to improve the Time to Achieve Lock and reduce the steady-state error. In addition, we evaluate the filter design into PLL scheme with an RTL-SDR device to demonstrate the performance noise in the receive signal; consequently, this is adapted to other high-performance FPGA technologies for radio signal processing.

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Ortega A, Inga J, Lamadrid D. Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems. En Robles-Bykbaev V, Mula J, Reynoso-Meza G, editores, Intelligent Technologies: Design and Applications for Society - Proceedings of CITIS 2022. Springer Science and Business Media Deutschland GmbH. 2023. p. 182-190. (Lecture Notes in Networks and Systems). doi: 10.1007/978-3-031-24327-1_16

Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems

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