Flag Based All Digital Timing Recovery

Daniel Cardenas; German Arevalo

doi:10.1109/CHILECON47746.2019.8987987

Flag Based All Digital Timing Recovery

Daniel Cardenas
, German Arevalo

Grupo de Investigación en Electrónica y Telemática (GIETEC)

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución de conferencia › revisión exhaustiva

2 Citas (Scopus)

Resumen

We implemented an all-digital timing recovery i.e. without a VCO, that works in case the receiver is faster or slower than the transmitter and with no need of decimation, unlike other implementations. This system takes advantage of and is suitable for parallel structures.

Idioma original	Inglés
Título de la publicación alojada	IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019
Editorial	Institute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)	9781728131856
DOI	https://doi.org/10.1109/CHILECON47746.2019.8987987
Estado	Publicada - nov. 2019
Evento	2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019 - Valparaiso, Chile Duración: 13 nov. 2019 → 27 nov. 2019

Serie de la publicación

Nombre	IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019

Conferencia

Conferencia	2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019
País/Territorio	Chile
Ciudad	Valparaiso
Período	13/11/19 → 27/11/19

Nota bibliográfica

Publisher Copyright:
© 2019 IEEE.

Acceder al documento

10.1109/CHILECON47746.2019.8987987

Otros archivos y enlaces

https://www.scopus.com/pages/publications/85081062473

Procesamiento Digital de Señales en Circuitos de Micro y Nanoelectrónica Digital Reconfigurable para Comunicaciones y Control
Arevalo Bermeo, G. V. (Investigador principal), Procel Moya, L. M. (Investigador Externo) & Cárdenas López, D. F. (Investigador Externo)
23/03/19 → 23/03/20
Proyecto: Investigación y Desarrollo

Citar esto

Cardenas, D., & Arevalo, G. (2019). Flag Based All Digital Timing Recovery. En IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019 Artículo 8987987 (IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CHILECON47746.2019.8987987

Cardenas, Daniel ; Arevalo, German. / Flag Based All Digital Timing Recovery. IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019).

@inproceedings{902133853b3f4ac68d6dfa19a24f3e48,

title = "Flag Based All Digital Timing Recovery",

abstract = "We implemented an all-digital timing recovery i.e. without a VCO, that works in case the receiver is faster or slower than the transmitter and with no need of decimation, unlike other implementations. This system takes advantage of and is suitable for parallel structures.",

keywords = "digital CDR, PLL, timing recovery",

author = "Daniel Cardenas and German Arevalo",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019 ; Conference date: 13-11-2019 Through 27-11-2019",

year = "2019",

month = nov,

doi = "10.1109/CHILECON47746.2019.8987987",

language = "English",

series = "IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019",

address = "United States",

}

Cardenas, D & Arevalo, G 2019, Flag Based All Digital Timing Recovery. En IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019., 8987987, IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019, Valparaiso, Chile, 13/11/19. https://doi.org/10.1109/CHILECON47746.2019.8987987

Flag Based All Digital Timing Recovery. / Cardenas, Daniel; Arevalo, German.
IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8987987 (IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución de conferencia › revisión exhaustiva

TY - GEN

T1 - Flag Based All Digital Timing Recovery

AU - Cardenas, Daniel

AU - Arevalo, German

PY - 2019/11

Y1 - 2019/11

N2 - We implemented an all-digital timing recovery i.e. without a VCO, that works in case the receiver is faster or slower than the transmitter and with no need of decimation, unlike other implementations. This system takes advantage of and is suitable for parallel structures.

AB - We implemented an all-digital timing recovery i.e. without a VCO, that works in case the receiver is faster or slower than the transmitter and with no need of decimation, unlike other implementations. This system takes advantage of and is suitable for parallel structures.

KW - digital CDR

KW - PLL

KW - timing recovery

UR - https://www.scopus.com/pages/publications/85081062473

U2 - 10.1109/CHILECON47746.2019.8987987

DO - 10.1109/CHILECON47746.2019.8987987

M3 - Conference contribution

AN - SCOPUS:85081062473

T3 - IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019

BT - IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019

Y2 - 13 November 2019 through 27 November 2019

ER -

Cardenas D, Arevalo G. Flag Based All Digital Timing Recovery. En IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8987987. (IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019). doi: 10.1109/CHILECON47746.2019.8987987

Flag Based All Digital Timing Recovery

Resumen

Serie de la publicación

Conferencia

Nota bibliográfica

Acceder al documento

Otros archivos y enlaces

Huella

Proyectos

Procesamiento Digital de Señales en Circuitos de Micro y Nanoelectrónica Digital Reconfigurable para Comunicaciones y Control

Citar esto