Flag Based All Digital Timing Recovery

Daniel Cardenas; German Arevalo

doi:10.1109/CHILECON47746.2019.8987987

Flag Based All Digital Timing Recovery

Daniel Cardenas, German Arevalo

Electronics and Telematics Research Group (GIETEC)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

We implemented an all-digital timing recovery i.e. without a VCO, that works in case the receiver is faster or slower than the transmitter and with no need of decimation, unlike other implementations. This system takes advantage of and is suitable for parallel structures.

Original language	English
Title of host publication	IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728131856
DOIs	https://doi.org/10.1109/CHILECON47746.2019.8987987
State	Published - Nov 2019
Event	2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019 - Valparaiso, Chile Duration: 13 Nov 2019 → 27 Nov 2019

Publication series

Name	IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019

Conference

Conference	2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019
Country/Territory	Chile
City	Valparaiso
Period	13/11/19 → 27/11/19

Bibliographical note

Funding Information:
Submitted 19 June 2019. This work was supported in part by the TelecommunicationsResearch Group at Universidad Politécnica Salesiana, Ecuador. D. Cardenas is with Geophysics Institute, Escuela Politécnica Nacional, Quito, Ecuador (email: dcardenas@igepn.edu.ec). G. Arévalo is with Department of Telecommunications, Universidad Politécnica Salesiana, Quito, Ecuador (email: garevalo@ups.edu.ec)

Publisher Copyright:
© 2019 IEEE.

Keywords

digital CDR
PLL
timing recovery

Access to Document

10.1109/CHILECON47746.2019.8987987

Cite this

Cardenas, D., & Arevalo, G. (2019). Flag Based All Digital Timing Recovery. In IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019 Article 8987987 (IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CHILECON47746.2019.8987987

Cardenas, Daniel ; Arevalo, German. / Flag Based All Digital Timing Recovery. IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019).

@inproceedings{902133853b3f4ac68d6dfa19a24f3e48,

title = "Flag Based All Digital Timing Recovery",

abstract = "We implemented an all-digital timing recovery i.e. without a VCO, that works in case the receiver is faster or slower than the transmitter and with no need of decimation, unlike other implementations. This system takes advantage of and is suitable for parallel structures.",

keywords = "digital CDR, PLL, timing recovery",

author = "Daniel Cardenas and German Arevalo",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019 ; Conference date: 13-11-2019 Through 27-11-2019",

year = "2019",

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doi = "10.1109/CHILECON47746.2019.8987987",

language = "English",

series = "IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019",

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Cardenas, D & Arevalo, G 2019, Flag Based All Digital Timing Recovery. in IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019., 8987987, IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019, Valparaiso, Chile, 13/11/19. https://doi.org/10.1109/CHILECON47746.2019.8987987

Flag Based All Digital Timing Recovery. / Cardenas, Daniel; Arevalo, German.
IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8987987 (IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - We implemented an all-digital timing recovery i.e. without a VCO, that works in case the receiver is faster or slower than the transmitter and with no need of decimation, unlike other implementations. This system takes advantage of and is suitable for parallel structures.

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KW - PLL

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DO - 10.1109/CHILECON47746.2019.8987987

M3 - Conference contribution

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BT - IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019

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Cardenas D, Arevalo G. Flag Based All Digital Timing Recovery. In IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8987987. (IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019). doi: 10.1109/CHILECON47746.2019.8987987

Flag Based All Digital Timing Recovery

Abstract

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Bibliographical note

Keywords

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