Flag Based All Digital Timing Recovery

Daniel Cardenas, German Arevalo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We implemented an all-digital timing recovery i.e. without a VCO, that works in case the receiver is faster or slower than the transmitter and with no need of decimation, unlike other implementations. This system takes advantage of and is suitable for parallel structures.

Original languageEnglish
Title of host publicationIEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728131856
DOIs
StatePublished - Nov 2019
Event2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019 - Valparaiso, Chile
Duration: 13 Nov 201927 Nov 2019

Publication series

NameIEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019

Conference

Conference2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, CHILECON 2019
Country/TerritoryChile
CityValparaiso
Period13/11/1927/11/19

Keywords

  • digital CDR
  • PLL
  • timing recovery

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