Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems

Andres Ortega; Juan Inga; Diego Lamadrid

doi:10.1007/978-3-031-24327-1_16

Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems

Andres Ortega
, Juan Inga
, Diego Lamadrid

Research Group in Telecommunications and Telematics (GITEL)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Nowadays the toolchain for innovating wireless systems technology has a high growth rate with the inclusion of prototyping radio systems. The trend is to migrate toward Software Defined Radio (SDR) devices due to low complexity design, implementation, and speed of data transmission of radio resources. In this context, we highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation. The digital filter Type 2 is adapted to the PLL scheme to improve the Time to Achieve Lock and reduce the steady-state error. In addition, we evaluate the filter design into PLL scheme with an RTL-SDR device to demonstrate the performance noise in the receive signal; consequently, this is adapted to other high-performance FPGA technologies for radio signal processing.

Original language	English
Title of host publication	Lecture Notes in Networks and Systems
Subtitle of host publication	Design and Applications for Society - Proceedings of CITIS 2022
Editors	Vladimir Robles-Bykbaev, Josefa Mula, Gilberto Reynoso-Meza
Publisher	Springer Science and Business Media Deutschland GmbH
Pages	182-190
Number of pages	9
ISBN (Print)	9783031243264
DOIs	https://doi.org/10.1007/978-3-031-24327-1_16
State	Published - 2023
Event	8th International Conference on Science, Technology and Innovation for Society, CITIS 2022 - Guayaquil, Ecuador Duration: 22 Jun 2022 → 24 Jun 2022

Publication series

Name	Lecture Notes in Networks and Systems
Volume	607 LNNS

Conference

Conference	8th International Conference on Science, Technology and Innovation for Society, CITIS 2022
Country/Territory	Ecuador
City	Guayaquil
Period	22/06/22 → 24/06/22

Bibliographical note

Publisher Copyright:
© 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

Keywords

5G/6G
Loop Filter
PLL
RTL-SDR
Steady state

CACES Knowledge Areas

216A Network and Database Design and Administration
417A Electronics, Automation and Sound

Access to Document

10.1007/978-3-031-24327-1_16

Cite this

Ortega, A., Inga, J., & Lamadrid, D. (2023). Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems. In V. Robles-Bykbaev, J. Mula, & G. Reynoso-Meza (Eds.), Lecture Notes in Networks and Systems: Design and Applications for Society - Proceedings of CITIS 2022 (pp. 182-190). (Lecture Notes in Networks and Systems; Vol. 607 LNNS). Springer Science and Business Media Deutschland GmbH. https://doi.org/10.1007/978-3-031-24327-1_16

Ortega, Andres ; Inga, Juan ; Lamadrid, Diego. / Discrete Loop Filter for Time-Synchronization : An Approach from Design to Real Implementation with RTL-SDR Systems. Lecture Notes in Networks and Systems: Design and Applications for Society - Proceedings of CITIS 2022. editor / Vladimir Robles-Bykbaev ; Josefa Mula ; Gilberto Reynoso-Meza. Springer Science and Business Media Deutschland GmbH, 2023. pp. 182-190 (Lecture Notes in Networks and Systems).

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abstract = "Nowadays the toolchain for innovating wireless systems technology has a high growth rate with the inclusion of prototyping radio systems. The trend is to migrate toward Software Defined Radio (SDR) devices due to low complexity design, implementation, and speed of data transmission of radio resources. In this context, we highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation. The digital filter Type 2 is adapted to the PLL scheme to improve the Time to Achieve Lock and reduce the steady-state error. In addition, we evaluate the filter design into PLL scheme with an RTL-SDR device to demonstrate the performance noise in the receive signal; consequently, this is adapted to other high-performance FPGA technologies for radio signal processing.",

keywords = "5G/6G, Loop Filter, PLL, RTL-SDR, Steady state",

author = "Andres Ortega and Juan Inga and Diego Lamadrid",

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series = "Lecture Notes in Networks and Systems",

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Ortega, A, Inga, J & Lamadrid, D 2023, Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems. in V Robles-Bykbaev, J Mula & G Reynoso-Meza (eds), Lecture Notes in Networks and Systems: Design and Applications for Society - Proceedings of CITIS 2022. Lecture Notes in Networks and Systems, vol. 607 LNNS, Springer Science and Business Media Deutschland GmbH, pp. 182-190, 8th International Conference on Science, Technology and Innovation for Society, CITIS 2022, Guayaquil, Ecuador, 22/06/22. https://doi.org/10.1007/978-3-031-24327-1_16

Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems. / Ortega, Andres; Inga, Juan; Lamadrid, Diego.
Lecture Notes in Networks and Systems: Design and Applications for Society - Proceedings of CITIS 2022. ed. / Vladimir Robles-Bykbaev; Josefa Mula; Gilberto Reynoso-Meza. Springer Science and Business Media Deutschland GmbH, 2023. p. 182-190 (Lecture Notes in Networks and Systems; Vol. 607 LNNS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Nowadays the toolchain for innovating wireless systems technology has a high growth rate with the inclusion of prototyping radio systems. The trend is to migrate toward Software Defined Radio (SDR) devices due to low complexity design, implementation, and speed of data transmission of radio resources. In this context, we highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation. The digital filter Type 2 is adapted to the PLL scheme to improve the Time to Achieve Lock and reduce the steady-state error. In addition, we evaluate the filter design into PLL scheme with an RTL-SDR device to demonstrate the performance noise in the receive signal; consequently, this is adapted to other high-performance FPGA technologies for radio signal processing.

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Ortega A, Inga J, Lamadrid D. Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems. In Robles-Bykbaev V, Mula J, Reynoso-Meza G, editors, Lecture Notes in Networks and Systems: Design and Applications for Society - Proceedings of CITIS 2022. Springer Science and Business Media Deutschland GmbH. 2023. p. 182-190. (Lecture Notes in Networks and Systems). doi: 10.1007/978-3-031-24327-1_16

Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems

Abstract

Publication series

Conference

Bibliographical note

Keywords

CACES Knowledge Areas

Access to Document

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Cite this